EEPROMs, as is known in the art, require specialized on-chip circuitry to electrically discharge their floating gates. Additionally, since the discharging circuitry is attached to the floating gate transistors on a byte-by-byte basis, the complexity of the chip increases proportionally with an increase in the number of bytes in the EEPROM. Furthermore, since the memory cells of the EEPROM are written and erased at the byte level, the updating of memory in EEPROM is a relatively slow process.
In order to remedy the problem associated with EEPROM, the industry responded with high-density non-volatile fast memory, such as flash memory. Unlike the EEPROM memory, the erasing circuitry in flash memory is moved to the periphery of the memory array. The location of the erasing circuitry at the periphery of the memory permits erasure of entire blocks of data using in-circuit wiring. Thus, rather than erasing byte-by-byte, flash memory is erased and rewritten in large blocks of, for example, 8 kilobytes (K) to 128K. The block erasure and rewriting of flash memory results in faster performance of flash memory when compared to the performance of the EEPROM. Additionally, by moving the erasing circuitry to the periphery of the memory array, greater chip density is achievable than that of the EPROM or the EEPROM. Moreover, different configurations of flash memory (e.g., NAND configurations and NOR configurations) allow for rearrangement of a bit line and a word line. The rearrangement of bit lines and word lines permits balancing of chip density with chip processing speed.
Unfortunately, the complexity of the erasing circuitry is still present due to the nature of flash memory. Furthermore, a relatively high voltage is typically required to erase flash memory. Also, the aggregate cost of the erasing circuitry in flash memory is fairly significant, thereby making flash memory relatively expensive.
In view of the deficiencies associated with flash memory, a need exists in the art.